diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 8125804..dd61fe0 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -160,7 +160,6 @@
 
 static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
 					   struct clk *parent,
-					   const struct cpg_core_clk *core,
 					   u32 mul_reg, u32 mult, u32 div,
 					   char *name)
 {
@@ -175,8 +174,8 @@
 
 	rate = (gen3_clk_get_rate64(parent) * mult) / div;
 
-	debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
-	      __func__, __LINE__, name, core->parent, mult, div, rate);
+	debug("%s[%i] %s clk: mult=%u div=%u => rate=%llu\n",
+	      __func__, __LINE__, name, mult, div, rate);
 	return rate;
 }
 
@@ -230,56 +229,56 @@
 		return -EINVAL;
 
 	case CLK_TYPE_GEN3_MAIN:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						0, 1, pll_config->extal_div,
 						"MAIN");
 
 	case CLK_TYPE_GEN3_PLL0:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						CPG_PLL0CR, 0, 0, "PLL0");
 
 	case CLK_TYPE_GEN3_PLL1:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						0, pll_config->pll1_mult,
 						pll_config->pll1_div, "PLL1");
 
 	case CLK_TYPE_GEN3_PLL2:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						CPG_PLL2CR, 0, 0, "PLL2");
 
 	case CLK_TYPE_GEN3_PLL3:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						0, pll_config->pll3_mult,
 						pll_config->pll3_div, "PLL3");
 
 	case CLK_TYPE_GEN3_PLL4:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						CPG_PLL4CR, 0, 0, "PLL4");
 
 	case CLK_TYPE_GEN4_MAIN:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						0, 1, pll_config->extal_div,
 						"V3U_MAIN");
 
 	case CLK_TYPE_GEN4_PLL1:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						0, pll_config->pll1_mult,
 						pll_config->pll1_div,
 						"V3U_PLL1");
 
 	case CLK_TYPE_GEN4_PLL2X_3X:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						core->offset, 0, 0,
 						"V3U_PLL2X_3X");
 
 	case CLK_TYPE_GEN4_PLL5:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						0, pll_config->pll5_mult,
 						pll_config->pll5_div,
 						"V3U_PLL5");
 
 	case CLK_TYPE_FF:
-		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
 						0, core->mult, core->div,
 						"FIXED");